SK hynix accelerates development of 3D-stacked DRAM for AI systems

SK hynix has intensified the development of 3D-stacked DRAM-on-Logic for next-generation AI systems, including mobile devices. The company began recruiting engineers specializing in this technology through its American subsidiary in San Jose. SK hynix has already signed an agreement with a specific client to develop solutions based on this technology, indicating preparation for market introduction. The job posting specifies close collaboration with an American customer to jointly create 3D-stacked DRAM-on-Logic dies, where DRAM is vertically integrated directly on top of a system-on-chip. Unlike package-on-package (PoP) stacking, this method offers shorter interconnects, more I/O channels per area, reduced latency, improved energy efficiency, and better space utilization. The technology is aimed at AI systems requiring high memory bandwidth and low power consumption, where traditional PoP schemes are insufficient. One of the most promising application areas is mobile processors, with Apple and Qualcomm as leading developers. SK hynix's roadmap, presented at the TSMC technology symposium, includes further integration of memory with logic, such as applying advanced logic processes to HBM4 base dies and expanding to high-speed flash memory (HBF) and 3D-stacked DRAM-on-Logic. Meanwhile, Samsung is also conducting research on next-generation 3D DRAM, having published a joint paper with imec, KU Leuven and Lam Research on monolithic 3D DRAM architecture using oxide semiconductor channels, though the research remains at the simulation stage with no market plans announced.