AMD EPYC Venice Deep Dive: 256 Cores, 2nm TSMC, Two Sockets and Liquid Cooling as a Necessity

On July 22, 2026, at the AMD Advancing AI conference in San Francisco, AMD introduced the sixth-generation EPYC 9006 'Venice' server processors based on the Zen 6 architecture. The flagship EPYC 9996 offers 256 cores and 512 threads, up to 1 TB of L3 cache, and a 600W power envelope. The processors are manufactured on TSMC's 2nm process node (N2) using GAAFET nanosheet transistors, marking a shift from FinFET. The lineup is split across two new sockets: SP7 (with up to 16 DDR5-8000 memory channels and up to 1.6 TB/s bandwidth) and SP8 (8 channels, lower power). Both sockets support PCIe Gen 6 with up to 160 lanes in dual-socket configurations, and CXL 3.1. AMD has added new AVX-512 instructions for AI workloads, including AVX512_FP16 and AVX_VNNI_INT8. Compared to the previous EPYC 9005 'Turin' generation, the new chips offer an 80% performance and efficiency improvement and a 30% increase in thread density, according to AMD. The company also replaced the TDP metric with 'Default CPU Power.' AMD's own benchmarks show significant advantages over Intel Xeon 6980P and AWS Graviton5 in workloads like NGINX, TPCx-AI, and FAISS vector search. The author from Selectel notes that the move to two incompatible sockets increases platform complexity and costs, and that liquid cooling is becoming inevitable for 600W processors. Independent benchmarks are awaited, with Phoronix planning unrestricted testing.